Recently, a semiconductor integrated circuit (IC) such as a dynamic RAM is provided with an internal power supply by which the IC is driven. In this situation, a semiconductor IC is required to supply an output signal which is adapted to another IC driven by only an external power supply. Accordingly, a conventional semiconductor IC has an output gate for converting an output signal of an internal power supply level to an output signal of an external power supply level.
A first conventional output gate which is of a CMOS (complementary metal-oxide semiconductor) logic gate is composed of a P-MOS transistor connected at a source to an external power supply and an N-MOS transistor connected at source to ground. The common P-and-N MOS transistor are supplied at an input node of a common gate with an output signal of an internal circuit driven by an internal power supply.
In the first conventional output gate, when a signal of low level is supplied to the input node of the common gate, the P-MOS transistor is turned on and the N-MOS transistor is turned off, so that an output signal of the external power supply level is supplied from the output gate. On the other hand, when a signal of high level is supplied to the input node of the common gate, the P-MOS transistor is turned off and the N-MOS transistor is turned on, so that an output signal of ground level is supplied from the output gate.
According to the first conventional output gate, there is a disadvantage in that the first P-MOS transistor is not turned off completely even though a high level signal is supplied thereto, in such a state that the internal power supply level V.sub.IN T on which the supplied high level signal is based, and the Vcc meet the relation of "Vcc&gt;V.sub.IN T +V.sub.TP ", where V.sub.TP is a threshold voltage of the P-MOS transistor. As a result, a margin of the external power supply voltage is narrow.
A second conventional output gate by which the disadvantage of the first conventional output gate is removed includes a first P-MOS transistor and a first N-MOS transistor corresponding to the P-and-N MOS transistors of the first conventional output gate, a second N-MOS transistor connected at a gate to an internal power supply, at a source to a first node to which an input signal is supplied and at a drain to a second node which is connected to a gate of the first P-MOS transistor, and a second P-MOS transistor connected at a source to an external power supply, at a gate to an output of the CMOS gate and at a drain to the second node. The second P-MOS transistor supplies a feedback signal of an inverted level of the output signal to the gate of the first P-MOS transistor.
In the second conventional output gate, when the output signal of low level which is based on the high level input signal supplied through the second N-MOS transistor is supplied from the output gate to the second P-MOS transistor, it is turned on, so that a high level signal of the external voltage Vcc is supplied to the gate of the first P-MOS transistor through the second P-MOS transistor. Therefore, the first P-MOS transistor is completely turned off.
However, there is a disadvantage in that a transition time of the output signal "high" to "low" is long, because the first P-MOS transistor is not turned off completely before the external power supply voltage is supplied to the gate of the first P-MOS transistor. Therefore, a margin of the external power supply voltage of the semiconductor IC is narrow.